Peter Giacomini

Vice President - Engineering (Founder)

Mr. Giacomini has 27 years of experience in all phases of the development cycle for cutting edge telecommunications, consumer products, and electronics systems. His product development experience includes system level architecture definition; hardware, firmware, and software design; manufacturing support; field support; and leading development teams. Since its inception, he has been a member (and co-founder) of the EnCADIS Design, Inc. team working on various developments in the Telecom, Datacom, Consumer, and Medical electronics fields. For 2 years prior to joining EnCADIS, he had been employed by Parama Networks, Inc., where he was a member of a team that developed and implemented the system architecture for a carrier-class telecom system that supports SONET rates up to OC768 and various non-SONET data interfaces (Gigabit Ethernet, Fiber channel, etc.). In addition, he performed various hardware development (schematic capture; board lay-out; critical net hand-routing; and design and debug of a complex high-speed FPGA with various subsystems and interfaces) and tool support (CAD tool installation and administration, script generation, etc.) functions. During the year prior to joining Parama, he was a founder and architecture/development team member for Broadspider Networks, Inc., who developed QoS-based data products. His functions included evaluation and support of tools (HW CAD tools, SW development environments, Source change control systems, MR systems). During his 18 years at AT&T/Lucent Technologies - Bell Laboratories, he led projects based on innovative architectures using leading edge design techniques. He developed networking products for the Network Systems and Advanced Networking divisions (including Datakit VCS, BNS2000, and PacketStar IP Router/Switch), which supported ATM, Frame Relay, SMDS, TCP/IP and proprietary protocols. He managed a large percentage of the development from architecture definition through successful product introduction and manufacturing and field support. He also introduced modern development techniques such as HDL design, simulation techniques, and FPGA to ASIC conversions into these organizations causing the techniques to become an accepted part of the design methodologies. Just prior to leaving Bell Laboratories, he was a member of the team that developed the 20Gb/s and 54Gb/s switch fabrics for the PacketStar 6404 and 6408 router/ switches. During the PacketStar development, he participated in architecture definition, FPGA development, board-level simulation, and hardware/firmware debug. He designed a high-density and high-speed FPGA for this system that was used by major FPGA and synthesis tools vendors as a reference design to demonstrate their products capabilities. Mr. Giacomini received a Technical Diploma in Electrical Engineering Technology for DeVry Institute, a Bachelor of Arts degree in Computer Science from Rutgers University, New Brunswick, NJ; and a Master of Science degree in Computer Science from Stevens Institute in Hoboken , NJ. In addition, Mr. Giacomini has several patents pending for telecom systems and hardware development techniques.